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Andy's avatar
Andy
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7 years ago

JESD204B Rx Phase Compensation FIFO full

I working on a JESD204B interface between an ADC and a Arria V GZ FPGA. The hardware is a TI TSW14J56EVM and a ADS54J54EVM.

I have two clock inputs; a 100MHz clock that I'm using for a NIOS core and the avalon interfaces of the JESD204BIP and the reconfiguration controller; and a 125MHz clock that connects directly (no PLL) to the JESD204B IP pll_ref_clk and the rxLink_clk. The 125MHz clock is also used to clock data from the JESD204B IP's Avalon-ST interface. The 100MHz and the 125MHz clocks are derived from different sources.

The JESD204B link is not reliably initialising, it has done a few times, but generally doesn't.

Using the JESD204B's avalon-MM interface, I can see that the one of the PHY's phase compensation FIFOs is becoming full. Does anyone have any advice on what might be causing this?

Many thanks

Andy

3 Replies

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    7 years ago
    Andy, My apologies for the delayed first response by almost 10 days. I missed your case as I had another case with similar description. I will provide timely update moving forward. Currently you are sharing the pll reference clock and rxlink_clk. If you are not using Subclass 1, then the recommendation is to connect rxphy_clk as input to rxlink_clk instead of using the same clock as PLL reference clock. This should solve your Phase Comp FIFO being full issue. However, there could be more reasons why your link initialization is not stable. This could require some debug. Hence, could you let me know which state (CGS or ILS phase) the link initialization fails, so I could help debug it. If possible, please signal tap the following signals so I could assist you to debug the issue; -rx_islockedtodata -pll_locked -sync_n -sysref -dev_sync_n (both tx and rx) -jesd204_tx_link_data -jesd204_tx_link_ready -jesd204_tx_frame_ready -jesd204_rx_link_valid -jesd204_tx_frame_error -csr_lane_powerdown (both tx and rx) -jesd204_rx_link_data -jesd204_rx_link_ready -jesd204_rx_frame_error -jesd204_rx_link_valid -jesd204_rx_int -dev_lane_alligned -alldev_lane_alligned Regards, Nathan
    • Andy's avatar
      Andy
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      7 years ago

      Hi Nathan,

      Thanks for the response. Don't worry about the delay in replying, I imagine keeping on top of all the forum posts is quite a task.

      Since posting I've managed to get the JESD204B link reliably connecting. There were two issues. The first is I had the reset controller IP incorrectly configured. I had the clock frequency parameter wrong (an embarrassing mistake that one!). Second, I have now implemented a PLL to generate the rxlink_clk.

      Originally I had a 125MHz clock coming into the FPGA that was driving both the pll_ref_clk and the rxlink_clk (this still didn't work with the reset controller parameter corrected).

      I've now changed that external clock source to 250 MHz. I've reconfigured the JESD IP for a 250 MHz clock and (as stated above) added a PLL to generate 125 MHz from the 250 MHz for the rxlink_clk.

      In all cases, rxphy_clk is unused/disconnected.

      I am using JESD204B subclass 1. I don't understand the problem with my original clock connections, with the same 125 MHz clock connecting to both pll_ref_clk and the rxlink_clk.

      Thanks

      Andy

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    7 years ago
    Hie Andy, Thanks for your understanding. Since you are using subclass 1, then connecting both pll_ref_clk to rxlink_clk should be ok. The rxhy_clk does not need to be used. Anyway, it seems you have managed to complete JESD204B link initialization. Hence, could you let me know if you are facing any other issues right now. Regards, Nathan