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Andy's avatar
Andy
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7 years ago

JESD204B Rx Phase Compensation FIFO full

I working on a JESD204B interface between an ADC and a Arria V GZ FPGA. The hardware is a TI TSW14J56EVM and a ADS54J54EVM. I have two clock inputs; a 100MHz clock that I'm using for a NIOS core and...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago
Hie Andy, Thanks for your understanding. Since you are using subclass 1, then connecting both pll_ref_clk to rxlink_clk should be ok. The rxhy_clk does not need to be used. Anyway, it seems you have managed to complete JESD204B link initialization. Hence, could you let me know if you are facing any other issues right now. Regards, Nathan