New ContributorJESD204B RX PCFIFO Full / TX PCFIFO Empty
I'm currently trying to implement a loop back test using the JESD204B IP Core on an Arria 10 module.
The core is configured to run with a reference clock of 100 MHz and a data rate of 6000 Mbps. I provide a 100 MHz device clock externally and route it through an internal PLL to generate the frame and link clock of same frequency. The device clock is free-running and permanently connected to the JESD-IP-Core, while all other clocks can be held in reset through the PLL.
After asserting all resets, I go through the "wake up"-sequence of the core, which is described in ug_jesd204b p. 71 and p. 73.
After making sure both link and frame clock are stable i deassert the XCVR-Reset and shortly after the PLL locked signal goes high. What baffles me is, that even though avs, link and frame reset are still active (low), the pcfifo_full of the RX channel and pcfifo_empty of TX channel get asserted. These flags aren't getting cleared after going through the complete reset sequence and thus the link is not valid after completing the sequence (according to the documentation of rx_err0 in the RX register map), even though the valid signals are being asserted.
The reset-sequence is completely controlled via a program running in Linux on the HPS, so reset durations shouldn't be a problem.
I've attached a CSV with hopefully all the relevant waveforms from the logic analyzer.
reset_out0 is the reset for the frame and link clock PLL and reset_out1 is the reset for the XCVR reset controller.
Many thanks for your help.
