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CHebl's avatar
CHebl
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6 years ago

JESD204B RX PCFIFO Full / TX PCFIFO Empty

I'm currently trying to implement a loop back test using the JESD204B IP Core on an Arria 10 module. The core is configured to run with a reference clock of 100 MHz and a data rate of 6000 Mbps. I p...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago

Hie,

The csr_pcfifo_full_err are debug registers that

are when rx_err is observed. This are not direct status flags but registered; hence it might not be cleared until CSR registers are configured. Please check if the CSR registers are configured. Hence, I will not recommend to ignore this flags.

Anyway the Arria 10 Phy user guide mentioned when using enhanced PCS, you can ignore the Phase Comp FIFO flag signal when used in Phase Comp FIFO mode. JESD IP does not use the Enhanced PCS hence its not contradicting between JESD IP user guide and Arria 10 Transceiver Phy user guide.

Please use the csr_sysref_lmfc_err ro check whether SYSREF period matches the LMFC period.

Even in Subclass 1, CGS will completed as long as Rx able to see K28.5 character. As long as sync_n is deasserted, sysref is provided to converter and JESD204B IP, the Rx can start looking for K28.5 and completed CGS.

Regards,

Nathan