In the Intel Arria 10 Transceiver PHY User Guide on p. 79 and p. 80 it is written, that the mentioned flags can be ignored. This is conflicting to mentioned documentation of the register maps of the JESD-IP Core.
Can I still ignore these flags?
Also my problems might be due to SYNC~ being asserted before SYSREF has been registered and thus after LMFC alignment SYNC~ gets asserted.
Now I'm going to look into why the CGS completes in Subclass 1 Mode without SYSREF being registered.
The PHY Guide can be found here:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf
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