Issue with RSU module or corrupted flash?

Hi Jcole,

Could you please refer to and try the example provided in the - Cyclone 10 LP Remote System Upgrade Design Example User Guide. The mentioned design example can be found here: Intel® Cyclone® 10 LP FPGA – Remote System Update Design Example

Also, note that to ensure the successful reconfiguration between the pages, assert the RU_nCONFIG signal for a minimum of 250 ns. This is equivalent to strobing the reconfig input of the Altera Remote Update IP core high for a minimum of 250 ns. If there is an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (based on mode and error condition) by setting the control register accordingly. You can refer to Intel® Cyclone® 10 LP user guide for more detailed information.

Regards,

Fakhrul