Jcole
Occasional Contributor
2 years agoIssue with RSU module or corrupted flash?
I have a RSU module in my boot-loader design running on the cyclone 10 LP eval board. I have a JIC file loaded with the boot-loader image at address 0x00, image 1 at address 0x400000, and image 2 at address 0x600000. Upon start up, the boot loader successfully loads and reconfigures the FPGA with image 1.
Once Image 1 is loaded, its design is to run an exact copy of the the boot-loader statemachine, but this time pointed at address 0x00 (return to bootload). An issue arises when the reconfig signal is pulsed, the board goes into an unresponsive state and even remains in this state during power cycles. To fix the board, I must program the FPGA with a new image file (Sof or Jic).
Any reason why the FPGA would become unresponsive?