New ContributorMy device is an Arria 10 SOC. I'm using the GPIO Intel FPGA IP 18.0 core, set up as DDIO with separate input/output clocks. I'd like to use the clock enable (port), but I don't see whether that enable port is for the inclock or outclock.
Regular ContributorHi,
I apologize for the late response,
When turning the Enable clock enable port ON, this allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
I hope this answers you r question, let me know if you need more help.
Regular ContributorHi,
You may find more information regarding the port in our user guide here:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=15
New ContributorBut there are 2 clock ports: clkin and clkout. In order for me not to violate setup and hold requirements, should the clken port be driven synchronously by the clkin or clkout clock?
Regular ContributorHi,
For the GPIO input registers, the input I/O transfer will likely fail the hold time if you do not set the input delay chain.
For more info please read the Timing Closure Guidelines:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=21
Occasional ContributorHi,
This last reply did not really address the question which is "should the clken port be driven synchronously by the clkin or clkout clock?". Can you please answer that question?
Thanks,
Steve Zack (the FAE supporting this customer)
