Forum Discussion
EBERLAZARE_I_Intel
Regular Contributor
6 years agoHi,
For the GPIO input registers, the input I/O transfer will likely fail the hold time if you do not set the input delay chain.
For more info please read the Timing Closure Guidelines:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=21
SZack
Occasional Contributor
6 years agoHi,
This last reply did not really address the question which is "should the clken port be driven synchronously by the clkin or clkout clock?". Can you please answer that question?
Thanks,
Steve Zack (the FAE supporting this customer)