Forum Discussion
GZsch
New Contributor
New ContributorIs the CKE port for the INCLOCK or the OUTCLOCK?
My device is an Arria 10 SOC. I'm using the GPIO Intel FPGA IP 18.0 core, set up as DDIO with separate input/output clocks. I'd like to use the clock enable (port), but I don't see whether that enabl...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
For the GPIO input registers, the input I/O transfer will likely fail the hold time if you do not set the input delay chain.
For more info please read the Timing Closure Guidelines:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=21
SZack
Occasional Contributor
Occasional ContributorHi,
This last reply did not really address the question which is "should the clken port be driven synchronously by the clkin or clkout clock?". Can you please answer that question?
Thanks,
Steve Zack (the FAE supporting this customer)
