New Contributor
New ContributorBut there are 2 clock ports: clkin and clkout. In order for me not to violate setup and hold requirements, should the clken port be driven synchronously by the clkin or clkout clock?
Regular ContributorHi,
For the GPIO input registers, the input I/O transfer will likely fail the hold time if you do not set the input delay chain.
For more info please read the Timing Closure Guidelines:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=21
Occasional ContributorHi,
This last reply did not really address the question which is "should the clken port be driven synchronously by the clkin or clkout clock?". Can you please answer that question?
Thanks,
Steve Zack (the FAE supporting this customer)
Regular ContributorHi,
The direction to the CKE is an INPUT.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf#page=10
This CKE will be controlling the CLK(clkin) of the IP.
If you are using BiDir(Bi Directional data), then you will have CK_IN(clkin) and CK_OUT(clkout), which the CKE will be controlling both of clocked in and out.
Regular ContributorHi,
Do you have any additional questions?
The CKE is basically acts as a switch, controlling the CLK of the IP.
