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Altera_Forum's avatar
Altera_Forum
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17 years ago

InterNiche driver with Marvel 88E1111

good day.

[recapitulation from other thread]

i am using the cyclone iii development board (ef3c120f7807cn)

the samples included in the dev kit does not include any ethernet. therefore i changed the samples to include a tse mac using the marvel 88e111 instead.

i am getting the a "no free buffers for rx" after phy initialization

=============== Software License Reminder ================

This software project uses an unlicensed version of the NicheStack TCP/IP

Network Stack - Nios II Edition. If you want to ship resulting object

code in your product, you must purchase a license for this software from

Altera. For information go to: "http://www.altera.com/nichestack"

================================================== ===

Created "Inet main" task (Prio: 2)

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Your Ethernet MAC address is 00:07:ed:ff:cd:15

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x04000000

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 100, Duplex = Full

OK, x=7, CMD_CONFIG=0x01000000

MAC post-initialization: CMD_CONFIG=0x05000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

No free buffers for rx

No free buffers for rx

No free buffers for rx

After N Repetitions it Stops.

by suggestion from jakobjones it seems that the mac is receiving a packet and trying to allocate abuffer from the interniche stack.

my question is, if this is the reason how can i disable the the mac from sending all the packets to avoid swamping or how to increase the number of large buffers available, i am using version 9.0

thankyou!

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You can change the buffer size in ipport.h (system library / Debug / system description).

    But by default there are 30 buffers allocated, so it would mean that the MAC received at least 30 packets before having the chance to do anything. Do you have a lot of traffic going on that connexion?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Daixiwen.

    thankyou for your reply.

    Unfortunately I tried it also in an isolated network, without any trafic and stills show the same error.

    Even with the network cable un plugged after 3 attempts of Auto-Negotioation and checking for PHY Link... it ocurrs also.

    I will paste here the debug out.

    Your Ethernet MAC address is 00:07:ed:ff:cd:15

    prepped 1 interface, initializing...

    [tse_mac_init]

    INFO : TSE MAC 0 found at address 0x04000000

    INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]

    INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

    INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

    WARNING : PHY[0.0] - Auto-Negotiation FAILED

    MARVELL : Enabling auto crossover

    MARVELL : PHY reset

    INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

    WARNING : PHY[0.0] - Auto-Negotiation FAILED

    INFO : PHY[0.0] - Checking link...

    INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...

    INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

    WARNING : PHY[0.0] - Auto-Negotiation FAILED

    WARNING : PHY[0.0] - Link could not established

    WARNING : PHY[0.0] - Auto-Negotiation not completed! Speed = 100, Duplex = Full

    OK, x=0, CMD_CONFIG=0x01000000

    MAC post-initialization: CMD_CONFIG=0x05000203

    [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

    No free buffers for rx

    No free buffers for rx

    Any ideas?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I don't think it's software related. I rather think that something triggers the receive SGDMA...

    Can you check again the MII connection from the MAC to the external PHY, and the connection between the MAC and the RX SGDMA? Check also that the IRQs are set up correctly for the driver.

    You could also use Signaltap probes on the MII interface (receive part), and on the Avalon Stream between the MAC and the RX DMA, to check if anything unusual is happening there. Obviously when you remove the cable you shouldn't see any traffic there.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I will try to see the Signals with Signaltap.

    How can I check the IRQs setup?`I did in SOPC automatic IRQ asignment That should be enough isnt it? what else should I verify to validate they are correct?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi, I am posting here the sopc construction. Is it correct?

    sgdma descriptors conected to on_chip_ram

    and in/out Avalon Streamings to the DDR SDRAM via an Avalon-MM crossing bridge.

    The Phy rx signals seems to be correct. But I am lost in the signalTap while trying to follow the avalon there are to many signals I dont really know.

    Any sugestions on the signals I can track down to find why the No free buffers for rx is still happening?

    http://www.alteraforum.com/forum/attachment.php?attachmentid=1273&stc=1&d=1247583000

    Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The SOPC setup seems correct, but I wonder if you shouldn't rename the on_chip_ram to descriptor_memory. I know that earlier TSE drivers for Interniche (before Quartus 8.0) hardcoded the name of that memory, and I don't know if today's driver can figure automatically where to put the descriptors.

    By IRQ setup I meant checking that the IRQ number for the RX SGDMA (4) is correct in the software system.h, and that the driver is initialized with the correct value. But I don't see why it shouldn't...

    For the avalon stream to inspect, you can go into the SOPC system, "the_tse_mac" entity, and concentrate on the receive_* signals. Pay attention to the ready and startofpacket signals, to see if the MAC gives anything to the DMA.

    The irq signal from the_sgdma_rx could be interesting too.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What are your task priorities set to? In my experience, setting task priorities incorrectly can cause the sort of behavior you're seeing.

    - Ura
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi rubenc,

    I try ethernet marvell 88E1111 InterNiche in EP3C120F780, but in thread http://www.alteraforum.com/forum/showthread.php?t=3665&page=1

    it use cyclone EP3C25.

    it seem different component like dram, flash, and sram. so it will different in pin mapping.

    How are you configure pin in file .qsf ?

    if you don't mind can you post here your new design ethernet and how it configured.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    Is this problem fixed? I'm also facing same issue & not sure how to fix. I tried increasing the buffer size but didn't work.

    Samir
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    can you please answer this simple question Marvel Alaska 88e1111 is software programmable? or hardware programmable only by changing low high states on its pin?