Honored Contributor
Honored ContributorThe SOPC setup seems correct, but I wonder if you shouldn't rename the on_chip_ram to descriptor_memory. I know that earlier TSE drivers for Interniche (before Quartus 8.0) hardcoded the name of that memory, and I don't know if today's driver can figure automatically where to put the descriptors.
By IRQ setup I meant checking that the IRQ number for the RX SGDMA (4) is correct in the software system.h, and that the driver is initialized with the correct value. But I don't see why it shouldn't... For the avalon stream to inspect, you can go into the SOPC system, "the_tse_mac" entity, and concentrate on the receive_* signals. Pay attention to the ready and startofpacket signals, to see if the MAC gives anything to the DMA. The irq signal from the_sgdma_rx could be interesting too.
