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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago
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Intel FFT IP example design available ?

Helllo,

I works on Intel Arria10 EVM, I really need an FFT IP example design for my A10 project? I open my Quartus pro 19.2 (platform designer) , but fail to find where to generate an example design for FFT IP Core ? Pleade advise where to generate for my starter of FFT verification .

BTW: I need to build a 4096-point FFT / IFFT project in our own board.

Appreciate help~

  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

    https://www.mathworks.com/help/signal/ref/digitrevorder.html

    Hopefully this is helpful. Thank you.

6 Replies

  • JET60200's avatar
    JET60200
    Icon for Contributor rankContributor
    5 years ago

    @CheePin_C_Intel

    Hi CheePin, nice to @ u, since I see you had answered several FFT IP related questions here.

    When checking FFT IP UG : " 3.4.2.3. I/O Order " ,

    Natural order
    Digit Reverse
    Order

    I don't understand them very well, Can you give an explaination, and any example of "Natural ordr” / " Digit reverse order " ？ I have some incorrect FFT output in A10 project, so I wantto understand where may introduce error.

    Thanks in advance

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi,

      As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

      https://www.mathworks.com/help/signal/ref/digitrevorder.html

      Hopefully this is helpful. Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    I notice that you have another inquiry related to FFT example design generation. As a workaround, you can try to generate a simulation example design for FFT IP in older Quartus standard edition ie Q17.0. You can configure your FFT IP and then click on Generate Example Design.

    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin



  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.