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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago
Solved

Intel FFT IP example design available ?

Helllo, I works on Intel Arria10 EVM, I really need an FFT IP example design for my A10 project? I open my Quartus pro 19.2 (platform designer) , but fail to find where to generate an example de...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

    https://www.mathworks.com/help/signal/ref/digitrevorder.html

    Hopefully this is helpful. Thank you.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

https://www.mathworks.com/help/signal/ref/digitrevorder.html

Hopefully this is helpful. Thank you.

JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

thanks @，

we had addressed our issue, you can close the bug. Thanks for kindly help./