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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Intel DisplayPort Example Project Fails to Generate Simulation (Quartus Pro v19.1/v19.2)

Hi,

I am trying to generate the simulation HDL for the Intel DisplayPort example project for the Stratix 10. I am consistently getting the same error message (attached). I have tried changing the number of lanes, speed, Verilog/VHDL and with/without PCR and it always fails at the same spot.

I even tried upgrading from Quartus Pro v19.1 to v19.2 and it still failed. Am I doing something wrong? I cannot generate the simulation data for some of the bitec encrypted cores manually and this is the only way to do it.

Thanks,

DZuck1

9 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi, This looks like a known issue in Quartus Pro v19.1 that will be fixed in future Quartus release. Kindly confirm if you are using Windows platform to generate Display Port example design ? If yes, then I maybe able to share workaround fix to you via private message. Else you can also use Quartus Pro Linux version as workaround. Thanks. Regards, dlim
    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      Yes, I am using Windows to generate the example design.
  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    HI, I just pm you the workaround design fix. Thanks. Regards, dlim
    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      Thank you dlim! I am trying it out right now. Does this simulate the clkrec encrypted file?
  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    HI, Sorry, I am not quite sure. Perhaps you can try out and see. Typically I try out hardware testing directly on DisplayPort rather than using simulation due to variance of GPU and monitor. Thanks. Regards, dlim
    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      I am able to generate the simulation with the fixed file provided above.

      I noticed tin the s10_dp_demo.v generated for the simulation the bitec_clkrec core is commented out of the code. When I uncomment it, my simulator (Aldec Active-HDL) tells me that there is no simulation data (SPD file) for this core. Does Intel provide a simulation model for the bitec_clkrec core?

      Thanks!

      DZuck1

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    ​Hi DZuck1,

    Looks like you just discovered the missing sim model support.

    Basically, Intel DisplayPort IP has 3rd party IP design integrated into it which is all the bitec* related design files. So, the support for it is min as this is 3rd party design where Intel also doesn't have much control over it.

    Sorry and thanks for your understanding.

    Regards,

    dlim

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      Is there any plan to add this support in future Quartus releases? I asked Bitec and they said they do have a simulation model for the core but since I am using the Intel version of it they can’t give it to me directly.
  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi DZuck1,

    I am sorry.

    As of now, Intel has no plan to support further sim model.

    From Intel perspective, we always encourage customer to perform hardware testing on DisplayPort IP instead of running sim as DisplayPort has highly dependency on GPU selection and monitor selection.

    It's safer to test with actual hardware.

    Thanks.

    Regards,

    dlim