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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Intel DisplayPort Example Project Fails to Generate Simulation (Quartus Pro v19.1/v19.2)

Hi, I am trying to generate the simulation HDL for the Intel DisplayPort example project for the Stratix 10. I am consistently getting the same error message (attached). I have tried changing the n...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
HI, Sorry, I am not quite sure. Perhaps you can try out and see. Typically I try out hardware testing directly on DisplayPort rather than using simulation due to variance of GPU and monitor. Thanks. Regards, dlim
DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

I am able to generate the simulation with the fixed file provided above.

I noticed tin the s10_dp_demo.v generated for the simulation the bitec_clkrec core is commented out of the code. When I uncomment it, my simulator (Aldec Active-HDL) tells me that there is no simulation data (SPD file) for this core. Does Intel provide a simulation model for the bitec_clkrec core?

Thanks!

DZuck1