Honored ContributorHi,
I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someone give me a good type there or a Example for a IIR filter with LUT or with multiplie accumulate? Thanks.
Honored Contributormy workstation is a x64 OS Win 7 Prof with 8 GB RAM, thats not normaly that a program go out of memory.
Could you explain me how I can make settings in quartus or in dsp-builder for better work with the RAM? Is the solution maybe Quartus 9.2 with DSP-Builder 9.2? Thanks for your answer... http://www.alteraforum.com/forum//proweb/misc/progress.gifHonored ContributorDSP Builder is only built for MATLAB 32-bit so it cannot take advantage of your full 8GB of RAM. i imagine the call to Quartus II also runs the 32-bit Quartus binary.
Honored ContributorI found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred.
The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205. Now the consuption of my RAM are about 1200MB... Thanks...
