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Altera_Forum
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16 years ago

IIR in DSP-Builder with modified multiplier LUT or multiplie accumulate

Hi, I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someon...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred.

The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205.

Now the consuption of my RAM are about 1200MB...

Thanks...