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Altera_Forum
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16 years ago

IIR in DSP-Builder with modified multiplier LUT or multiplie accumulate

Hi, I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someon...
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Altera_Forum
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16 years ago

DSP Builder is only built for MATLAB 32-bit so it cannot take advantage of your full 8GB of RAM. i imagine the call to Quartus II also runs the 32-bit Quartus binary.