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Altera_Forum's avatar
Altera_Forum
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15 years ago

I2C Woes, Opencore and Terasic

I've been trying to get a functional I2C bus in my design for a while now with no luck. I've tried my own and a few open source cores. ALL of them have the same problem. I never receive ACKs. I cannot figure out for the life of me why not.

I'm working on my graduate work and this I2C problem wasn't supposed to be a problem. I've got no work done and can't progress until I can talk to my D5M camera (also, the D5M library I tried didn't work either). I know it's a problem with me, it's in my circuit somewhere but I must not be experienced enough to locate it.

I've posted a logic analyzer screenshot or my current design with the Terasic demo for the D5M. They get an ACK, I don't. I looked at the code that accompanies the demo but it's so obfuscated I don't see much hope in using it for my design. I can see what's going on: they're just controlling the line bit by bit, but they get ACKs!

I've also provided some code snippets. One is my own code implementing a downloaded IP that uses the wishbone bus, which I now have working aside from acknowledgements, and the Terasic demo for the D5M camera. Any help would be great. Also, if there's something I'm missing (which I'm sure is probably the case) about verilog assignments and driving bidirectional pins, where do I go for more help? I'm lost and out of ideas. Thanks everyone.

edit: I'd also like to point out I'm having the same issue with the on board audio chip (WM8731) on my DE2-115. The Altera demo works (ACKs) but my cores, as well as the University Program core, does not.

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would expect, that the I2C core has no problems to work with open drain SCL operation, which is according to the standard. It may be however a hardware related issue of a missing or too high resistance pull-up, or strong crosstalk from other signals (possibly SDA) to the SCL node. As long as no I2C device is utilizing clock stretching, push-pull drive of SCL shouldn't be a problem.

    P.S.: The I2C standard requires I2C devices to filter spikes at both bus lines. I'm missing this feature from the I2C core itself, however.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    P.S.: The I2C standard requires I2C devices to filter spikes at both bus lines. I'm missing this feature from the I2C core itself, however.

    --- Quote End ---

    That is very strict. Do you know of any core that does this?

    If the I2C device(s) are on on the same board or in the same case, I wouldn't bother. I would not even bother if it was over a cable of xx meter, as long as the cable is well designed.