In some examples,I can see they just add some timing constraints in sdc file,for example,"create_clock -period 1.552 [get_ports TenGbE_RefClk]".But PIN_AK7 is only a 100MHz clock described in DE5-Net User Manual.pdf,and in Signal Tap Logic Analyzer,it's really just 100MHz , I don't know why, anyone can help me? thanks!

HI, May I know are you referring to which Intel FPGA reference design or your own Quartus design ? Second, do you encounter this issue in which development kit board ? Third, can you configure the on board clock generator chip to generate the 322MHz clock to FPGA ? Thanks. Regards, dlim

Yes,maybe you are right,I need confige the oscillators

Hi, Thanks for the feedback. You are right, Eth 10G reference design is expecting either 322MHz or 644MHz refclk frequency but reference design is just to demo functionality of Ethernet 10G IP. We do expect user to configure the reference design FPGA pinout to match back with the board in used. For instance, Intel FPGA does have full reference design that already pre-configured to match with Stratix V Transceiver Signal Integrity Development board pinout in below link. https://fpgawiki.intel.com/wiki/Stratix_V_10G_Ethernet_and_10G_Base_R_PHY_Interoperability_Hardware_Demonstration_Design However, if you are using Terasic development kit board instead then pls feel free to contact Terasic for technical support via below email support@terasic.com Thanks. Regards, dlim

Thanks for your reply, I do generate a 322MHz clock.Now, I connect 10g MAC and 10gbase-r PHY appropriately, and I only configured the register 0x1200、0x1201 and 0x1202 of 10g MAC, the output interface of SFP is directly connected to it's input interface. However, the signal link_fault_status_xgmii_tx_data is always 01.I tryed to use csr_clk of 10g MAC in 50MHz、125MHz and156MHz, but it does not work,I don't know why?Is there anything other I forgot to configure???

Hi, It would be easier if you can try to bring up the 10G Ethernet using reference design. This helps to ensure you have all the setting configured correctly. Is it possible to try modify the wiki reference design that I shared to suit your board or consult terasic for 10G reference design that suit their board directly ? Some of the causes of local fault that I can think of is like below : 1) transceiver not lock or stuck in reset - check transceiver reset, clock and CDR lock and rx_ready signal 2) RX PCS alignment word lock or block lock operation is not completed yet you already blast out Tx data traffic - hold off TX data traffic transfer until RX sync is up 3) high BER on channel link - check the terasic board channel signal integrity and make sure you had tune all the PMA parameter correctly 4) Nothing wrong with your SFP module cable or loopback module 5) PCS internal FIFO overflow/underflow - unlikely will be your case here Thanks. Regards, dlim

I was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?

11 Replies

Deshi_Intel
Regular Contributor
6 years ago
HI, May I know are you referring to which Intel FPGA reference design or your own Quartus design ? Second, do you encounter this issue in which development kit board ? Third, can you configure the on board clock generator chip to generate the 322MHz clock to FPGA ? Thanks. Regards, dlim
- Teng
  New Contributor
  6 years ago
  Yes,maybe you are right,I need confige the oscillators
Deshi_Intel
Regular Contributor
6 years ago
Hi, Thanks for the feedback. You are right, Eth 10G reference design is expecting either 322MHz or 644MHz refclk frequency but reference design is just to demo functionality of Ethernet 10G IP. We do expect user to configure the reference design FPGA pinout to match back with the board in used. For instance, Intel FPGA does have full reference design that already pre-configured to match with Stratix V Transceiver Signal Integrity Development board pinout in below link. https://fpgawiki.intel.com/wiki/Stratix_V_10G_Ethernet_and_10G_Base_R_PHY_Interoperability_Hardware_Demonstration_Design However, if you are using Terasic development kit board instead then pls feel free to contact Terasic for technical support via below email support@terasic.com Thanks. Regards, dlim
- Teng
  New Contributor
  6 years ago
  Thanks for your reply, I do generate a 322MHz clock.
  Now, I connect 10g MAC and 10gbase-r PHY appropriately, and I only configured the register 0x1200、0x1201 and 0x1202 of 10g MAC, the output interface of SFP is directly connected to it's input interface. However, the signal link_fault_status_xgmii_tx_data is always 01.
  I tryed to use csr_clk of 10g MAC in 50MHz、125MHz and156MHz, but it does not work,I don't know why?
  Is there anything other I forgot to configure???
Deshi_Intel
Regular Contributor
6 years ago
Hi, It would be easier if you can try to bring up the 10G Ethernet using reference design. This helps to ensure you have all the setting configured correctly. Is it possible to try modify the wiki reference design that I shared to suit your board or consult terasic for 10G reference design that suit their board directly ? Some of the causes of local fault that I can think of is like below : 1) transceiver not lock or stuck in reset - check transceiver reset, clock and CDR lock and rx_ready signal 2) RX PCS alignment word lock or block lock operation is not completed yet you already blast out Tx data traffic - hold off TX data traffic transfer until RX sync is up 3) high BER on channel link - check the terasic board channel signal integrity and make sure you had tune all the PMA parameter correctly 4) Nothing wrong with your SFP module cable or loopback module 5) PCS internal FIFO overflow/underflow - unlikely will be your case here Thanks. Regards, dlim
- Teng
  New Contributor
  6 years ago
  Thanks for your reply,
  I read register 0x082 of transceiver, and the readdata is 0x00000084,rx_ready and tx_ready are all high level, it seems well,but the signal link_fault_status_xgmii_tx_data is still 01.
  My project is based on 10G reference design under install director.
Deshi_Intel
Regular Contributor
6 years ago
HI, Have you reviewed my earlier debug suggestions (1) to (5) and also tried the wiki page example design ? Thanks. Regards, dlim
- Teng
  New Contributor
  6 years ago
  I tried to simulate the example that you shared, but I got lots of errors.
  The value of register 0x082 indicate that HI_BER ,BLOCK_ LOCK,TX_FIFO_FULL,RX_FIFO_FULL,RX_SYNC_HEAD_ERROR,RX_SCRAMBLER_ERROR,RX__DATA_READY all in right status.
  So, how to verify other possible factors (1) to (5) above?
  Thanks.
Deshi_Intel
Regular Contributor
6 years ago
Hi,
For the sim error issue debug
This is referring to the wiki reference design that I shared with you earlier.
I test run the wiki design myself and the sim error that I saw was "missing sim library files". This is due to the wiki design doesn't go through the Quartus compilation stage yet.
Below is how you can fix the sim error issue (refer to attached pic as well)
Move the QSYS file to same hierarchy as Quartus project folder
Open QSYS, set verilog for simulation library, then click generate QSYS to generate the sim library file for the IP
Finally launch modelsim again and run the compile.tcl script and it should works this time
For the hardware debug suggestion 1 to 5
I am not quite sure which register 0x082 that you are referring to here. Can you elaborate further on this register ?
Before that, you should make sure the Ethernet design setting matches with your board hardware.
My instruction on debug suggestion 1 to 5 should be pretty clear. Any part that still confuse you ?
Thanks.
Regards,
dlim
Deshi_Intel
Regular Contributor
6 years ago
posted a file.
Deshi_Intel
Regular Contributor
6 years ago
posted a file.

Forum Discussion

I was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?

11 Replies

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