Forum Discussion
Teng
New Contributor
New ContributorI was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?
In some examples,I can see they just add some timing constraints in sdc file,for example,"create_clock -period 1.552 [get_ports TenGbE_RefClk]". But PIN_AK7 is only a 100MHz clock described in DE5...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
May I know are you referring to which Intel FPGA reference design or your own Quartus design ?
Second, do you encounter this issue in which development kit board ?
Third, can you configure the on board clock generator chip to generate the 322MHz clock to FPGA ?
Thanks.
Regards,
dlim
TengYes,maybe you are right,I need confige the oscillators
