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Teng's avatar
Teng
Icon for New Contributor rankNew Contributor
6 years ago

I was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?

In some examples,I can see they just add some timing constraints in sdc file,for example,"​create_clock -period 1.552 [get_ports TenGbE_RefClk]". But PIN_AK7 is only a 100MHz clock described in DE5...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Thanks for the feedback. You are right, Eth 10G reference design is expecting either 322MHz or 644MHz refclk frequency but reference design is just to demo functionality of Ethernet 10G IP. We do expect user to configure the reference design FPGA pinout to match back with the board in used. For instance, Intel FPGA does have full reference design that already pre-configured to match with Stratix V Transceiver Signal Integrity Development board pinout in below link. https://fpgawiki.intel.com/wiki/Stratix_V_10G_Ethernet_and_10G_Base_R_PHY_Interoperability_Hardware_Demonstration_Design However, if you are using Terasic development kit board instead then pls feel free to contact Terasic for technical support via below email support@terasic.com Thanks. Regards, dlim
Teng's avatar
Teng
Icon for New Contributor rankNew Contributor
6 years ago

Thanks for your reply, I do generate a 322MHz clock.

Now, I connect 10g MAC and 10gbase-r PHY appropriately, and I only configured the register 0x1200、0x1201 and 0x1202 of 10g MAC, the output interface of SFP is directly connected to it's input interface. However, the signal link_fault_status_xgmii_tx_data is always 01.

I tryed to use csr_clk of 10g MAC in 50MHz、125MHz and156MHz, but it does not work,I don't know why?

Is there anything other I forgot to configure???