Forum Discussion
Teng
New Contributor
New ContributorI was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?
In some examples,I can see they just add some timing constraints in sdc file,for example,"create_clock -period 1.552 [get_ports TenGbE_RefClk]". But PIN_AK7 is only a 100MHz clock described in DE5...
Deshi_Intel
Regular Contributor
Regular ContributorHi,
It would be easier if you can try to bring up the 10G Ethernet using reference design. This helps to ensure you have all the setting configured correctly.
Is it possible to try modify the wiki reference design that I shared to suit your board or consult terasic for 10G reference design that suit their board directly ?
Some of the causes of local fault that I can think of is like below :
1) transceiver not lock or stuck in reset - check transceiver reset, clock and CDR lock and rx_ready signal
2) RX PCS alignment word lock or block lock operation is not completed yet you already blast out Tx data traffic - hold off TX data traffic transfer until RX sync is up
3) high BER on channel link - check the terasic board channel signal integrity and make sure you had tune all the PMA parameter correctly
4) Nothing wrong with your SFP module cable or loopback module
5) PCS internal FIFO overflow/underflow - unlikely will be your case here
Thanks.
Regards,
dlim
TengThanks for your reply,
I read register 0x082 of transceiver, and the readdata is 0x00000084,rx_ready and tx_ready are all high level, it seems well,but the signal link_fault_status_xgmii_tx_data is still 01.
My project is based on 10G reference design under install director.
