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Teng's avatar
Teng
Icon for New Contributor rankNew Contributor
6 years ago

I was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?

In some examples,I can see they just add some timing constraints in sdc file,for example,"​create_clock -period 1.552 [get_ports TenGbE_RefClk]". But PIN_AK7 is only a 100MHz clock described in DE5...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
HI, Have you reviewed my earlier debug suggestions (1) to (5) and also tried the wiki page example design ? Thanks. Regards, dlim
  • Teng's avatar
    Teng
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​I tried to simulate the example that you shared, but I got lots of errors.

    The value of register 0x082 indicate that HI_BER ,BLOCK_ LOCK,TX_FIFO_FULL,RX_FIFO_FULL,RX_SYNC_HEAD_ERROR,RX_SCRAMBLER_ERROR,RX__DATA_READY all in right status.

    So, how to verify other possible factors (1) to (5) above?

    Thanks.