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Teng's avatar
Teng
Icon for New Contributor rankNew Contributor
6 years ago

I was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?

In some examples,I can see they just add some timing constraints in sdc file,for example,"​create_clock -period 1.552 [get_ports TenGbE_RefClk]". But PIN_AK7 is only a 100MHz clock described in DE5...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

For the sim error issue debug

  • This is referring to the wiki reference design that I shared with you earlier.
  • I test run the wiki design myself and the sim error that I saw was "missing sim library files". This is due to the wiki design doesn't go through the Quartus compilation stage yet.
  • Below is how you can fix the sim error issue (refer to attached pic as well)
    • Move the QSYS file to same hierarchy as Quartus project folder
    • Open QSYS, set verilog for simulation library, then click generate QSYS to generate the sim library file for the IP
    • Finally launch modelsim again and run the compile.tcl script and it should works this time

For the hardware debug suggestion 1 to 5

  • I am not quite sure which register 0x082 that you are referring to here. Can you elaborate further on this register ?
  • Before that, you should make sure the Ethernet design setting matches with your board hardware.
  • My instruction on debug suggestion 1 to 5 should be pretty clear. Any part that still confuse you ?

Thanks.

Regards,

dlim