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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to use the DDR3 SDRAM Controller with UniPHY (and the Avalon interface) SoCKit

Hello,

I'm using Quartus 13.1 and a terasic SocKit Cyclone V board.

I'm new to FPGA-programming so please excuse if my misunderstanding seems basic. :)

I want to build a Memory Controller in order to address the FPGA's DDR3 Memory with the ARM-processor, using Xillibus FIFOs. (This part works, I can send data to my FPGA's logic, manipulate them (like shifting bits etc.) and send them back to the ARM).

Now I created an DDR3 Sdram-Controller with UniPHY by using the MegaWizard. I got all parameters from a demostration-project provided by terasic using the same board. However the example is coded in Verilog and I'm only capable of reading/writing VHDL.

I don't know how I have to implement the provided interface. My Avalon interface has an address width of 26 bits and a data width of 128 bit, which stems from the memory parameters. But the DDR3 Words are 32 bit and 15 bit addresses, so how am I supposed to just write one word(32 bit). As far as I understood it, I only have to control the provided Avalon interface in order to read/write from/to the RAM, so do I have to translate all reading/writing requests to the size of the avalon interface?

I honestly find the documentation a little confusing to say the least so if you know any other sources of information I would be grateful.

Thanks in advance for any suggestions and/or clarifications.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    on the FPGA side it depends on the configuration of the controller how big a word is.

    According to the specification of the DDR3 a word is 32-Bits for each cell. Address consists of 3 Bits for Bank, 15 Bits for Row and 10 for column. But because your controller uses 128-words, it erases the last two column bits, so you got 26-Bits instead of 28-Bits for addressing.

    So each address holds 128-Bits and you do not need to take care of the borders since the last two bits are erased.

    I am not sure what controller are you using (hard controller, soft controller or writing your own) but on every possibility there should be something like an be signal (for byte enable) where you set the value for the valid bytes. If you really want to hold multiple 32-Bit words in one 128-Bit address and can not write them at the same time, you need to use that be signal to mask the unused bytes and to not overwrite the previously written ones.

    Or simply hold one 32-Bit word in the 128-Bit word address spaces (will be OK if you do not need the whole 1 GB of the DDR).

    Where exactly do you have the 15-Bit address?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks for your reply!

    I was mistaken, the addressing of the DDR3 is not 15 bit, this was just the length of one Row. I definitely need the whole 1 GB of the DDR, and I will write my own controller but I want to use the generated interface. So due to the way the Avalon interface works , I have to translate between 32 bit and 128 bit words?! It would be pretty inefficient to read/write single 32 bit addresses of the FPGA's DDR from the ARM, wouldn't it? I can't really tell how 'wasteful' this might be, any idea if using the interface is even feasible for addressing the FPGA's RAM from the ARM.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    I definitely need the whole 1 GB of the DDR, and I will write my own controller but I want to use the generated interface.

    --- Quote End ---

    OK, I think we are talking about different things here. Let's clarify that.

    When you instanitate the UniPHY DDR3 RAM in Quartus or QSys, on the first options tabs you have the choice to set:

    - "Nothing" => Soft-Controller Interface will be provided and I think this is the interface you are talking about

    - Generate Phy Only => No Controller is synthesized and you get an Interface for a DDR3 Controller. The interface is called "afi"

    - Use Hard Memory Controller => This is new in Cyclone V and Arria V devices which have an hard controller integrated for better performance. You can configure an Multi-Port Front End (MPFE) which consist basically of multiple Avalon-MM interfaces.

    An own controller would be the hardest way. You need to take care of everything in the DDR3 like Activate Rows, Precharge Rows before you Activate another one in the Bank and all the timings needed like tRCD, tRTP and make sufficient refreshes within tREFI etc. I would recommend to use the hard controller.

    What is the bandwidth you need for your application?

    --- Quote Start ---

    I have to translate between 32 bit and 128 bit words?! It would be pretty inefficient to read/write single 32 bit addresses of the FPGA's DDR from the ARM, wouldn't it? I can't really tell how 'wasteful' this might be, any idea if using the interface is even feasible for addressing the FPGA's RAM from the ARM.

    --- Quote End ---

    Yes, with the soft-controller interface you need to translate a 32-Bit word into a 128-Bit word and since you need the whole 1GB, you also need to hold some information about which 32-Bit words in the 128-Bit word of the DDR3 addresses are occupied by your data to not overwrite them. You need to have a look at how a DDR3 works. It can read/write in BC4 (Burst Chop 4) or BL8 (Burst Length 8), which means a DDR3 can read/write 4x32-Bit words or 8x32-Bit words. You should try to use the hard-memory controller with the MPFE. You can configure it to have 32-Bit word interface, so you can use the whole 28-Bit address space easier, especially because it will mask the not used bytes when the write/read is handled as BC4 or BL8 to the DDR3. All in all this would be the easiest way...IMHO.