Honored Contributor
Honored ContributorHi,
on the FPGA side it depends on the configuration of the controller how big a word is. According to the specification of the DDR3 a word is 32-Bits for each cell. Address consists of 3 Bits for Bank, 15 Bits for Row and 10 for column. But because your controller uses 128-words, it erases the last two column bits, so you got 26-Bits instead of 28-Bits for addressing. So each address holds 128-Bits and you do not need to take care of the borders since the last two bits are erased. I am not sure what controller are you using (hard controller, soft controller or writing your own) but on every possibility there should be something like an be signal (for byte enable) where you set the value for the valid bytes. If you really want to hold multiple 32-Bit words in one 128-Bit address and can not write them at the same time, you need to use that be signal to mask the unused bytes and to not overwrite the previously written ones. Or simply hold one 32-Bit word in the 128-Bit word address spaces (will be OK if you do not need the whole 1 GB of the DDR). Where exactly do you have the 15-Bit address?
