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I definitely need the whole 1 GB of the DDR, and I will write my own controller but I want to use the generated interface.
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OK, I think we are talking about different things here. Let's clarify that.
When you instanitate the UniPHY DDR3 RAM in Quartus or QSys, on the first options tabs you have the choice to set:
- "Nothing" => Soft-Controller Interface will be provided and I think this is the interface you are talking about
- Generate Phy Only => No Controller is synthesized and you get an Interface for a DDR3 Controller. The interface is called "afi"
- Use Hard Memory Controller => This is new in Cyclone V and Arria V devices which have an hard controller integrated for better performance. You can configure an Multi-Port Front End (MPFE) which consist basically of multiple Avalon-MM interfaces.
An own controller would be the hardest way. You need to take care of everything in the DDR3 like Activate Rows, Precharge Rows before you Activate another one in the Bank and all the timings needed like tRCD, tRTP and make sufficient refreshes within tREFI etc. I would recommend to use the hard controller.
What is the bandwidth you need for your application?
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I have to translate between 32 bit and 128 bit words?! It would be pretty inefficient to read/write single 32 bit addresses of the FPGA's DDR from the ARM, wouldn't it? I can't really tell how 'wasteful' this might be, any idea if using the interface is even feasible for addressing the FPGA's RAM from the ARM.
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Yes, with the soft-controller interface you need to translate a 32-Bit word into a 128-Bit word and since you need the whole 1GB, you also need to hold some information about which 32-Bit words in the 128-Bit word of the DDR3 addresses are occupied by your data to not overwrite them. You need to have a look at how a DDR3 works. It can read/write in BC4 (Burst Chop 4) or BL8 (Burst Length 8), which means a DDR3 can read/write 4x32-Bit words or 8x32-Bit words. You should try to use the hard-memory controller with the MPFE. You can configure it to have 32-Bit word interface, so you can use the whole 28-Bit address space easier, especially because it will mask the not used bytes when the write/read is handled as BC4 or BL8 to the DDR3. All in all this would be the easiest way...IMHO.
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