How to use Nios ↔ Logic (Avalon mm Burst Transfer)

Hi,

Links below probably can help you out:

https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/introduction-to-the-interface-specifications.html (page 12)

http://www.cs.columbia.edu/~sedwards/classes/2008/4840/mnl_avalon_spec.pdf (page 72)

https://chowdera.com/2020/11/20201113203338313n.html

Video links:

https://www.youtube.com/watch?v=8GAqT3nzHeQ

https://www.youtube.com/watch?v=XTwPisYVyGg

Thanks,

Best Regards,

Sheng

Hi,

May I know any further update or consideration?

Thanks,

Best Regards,

Sheng

i just finish read Avalon mm Interface Spec Sheet . and i tried to make it.

1. I Dened like that Nios..

2. Nios Connection

when Connection Initial Nios Core Settings don't have Burst Count [32] so i tried to make it

- nios → Caches and Memory Interfaces → Data Cache → Add Burstcount signal to data_master → Enable

- Avalon MM -Slave <----> NIOS Core Data Master

: Burst_Count [32] <-----> : none

: ReadDataValid [1] <-----> : ReadDataValid [1]

: Addr [8] <----> : Addr [14] 

: Read [1] <----> : Read [1]

: Read_Data[32] <----> : Read_Data[32]

: wait_Request [1] <----> : wait_Request [1]

: write [1] <----->: write [1]

: Write_Data [32]  <----->: Write_Data [32] 

: none <-----> : Byte_Enable [4]

: none <----> : debug_mem_slave_debugaccess_to_roms [1]

for burst transfer is it good connection?

How about the byteenable signal (Master -> Slave)?

Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.