How to: Simulate the UniPHY memory controller interface with custom logic ?

Hello,

I've a custom logic which interfaces (in VHDL) with the Avalon interface on the UniPHY controller DDR2 SDRAM, I would like to test it, but I didn't results.

First I tried to edit/connect the simulation project (Verilog) whit my block, after some fails I went to the

IP Functional Simulations on External Memory Interface Handbook : Volume 4: Simulation, Timing Analysis, and Debugging.

Than tried to use the ddr2 block provide on the <project directory>\<variation name>_sim\<variation name>.vhd

but the problem is that I have some signals dedicate to memory exe: mem_a, mem_ba, mem_ck, mem_cke..... and I don't know hat to do whit it.

I went to memory vendors web site and found some memory models: they are in Verilog, second some signals like mem_ck are not compatible (one is std_logic_vector(1 downto 0) ? and the other is a normal wire)

Does any one know how can I test it ?

Thanks in advance

Rafa.