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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to: Simulate the UniPHY memory controller interface with custom logic ?

Hello, I've a custom logic which interfaces (in VHDL) with the Avalon interface on the UniPHY controller DDR2 SDRAM, I would like to test it, but I didn't results. First I tried to edit/...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Thanks for the tip, only to be more clear, I'll have to replace the : altera_merlin_slave_translator declaration with my block ?

Thanks

Rafa

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