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Honored Contributor
Honored ContributorHow to: Simulate the UniPHY memory controller interface with custom logic ?
Hello, I've a custom logic which interfaces (in VHDL) with the Avalon interface on the UniPHY controller DDR2 SDRAM, I would like to test it, but I didn't results. First I tried to edit/...
Altera_ForumHonored Contributor
Honored Contributorthe easiest way is to edit the Example Project generated by Quartus. it instantiates a basic memory model
the project is located a path similar to: ddr3_core\ddr3_core_example_design\simulation the file that instantiates the memory controller and example driver is what you want to edit. remove the example driver and add your logic: ddr3_core_example_sim_ddr3_core_example_sim_e0.v
