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Honored Contributor
Honored ContributorHow to: Simulate the UniPHY memory controller interface with custom logic ?
Hello, I've a custom logic which interfaces (in VHDL) with the Avalon interface on the UniPHY controller DDR2 SDRAM, I would like to test it, but I didn't results. First I tried to edit/...
Altera_ForumHonored Contributor
Honored Contributoryes, you should be able to ignore the d0_avl_translator_avalon_universal_master bus and just drive the if0_avl_translator_avalon_anti_slave bus
