How to implement a C routine to VHDL?

Question

Hi, I am trying to rewrite C routine for ethernet (sending of a packet) to VHDL. And I would like to know, how can I write command for setting up some configuration in ethernet driver registry. For example I have this function in C:  
void iow(unsigned int reg, unsigned int data) {
  IOWR(DM9000A_BASE,IO_addr,reg);
  usleep(STD_DELAY);
  IOWR(DM9000A_BASE,IO_data,data);
}
  Specifically without constant: 
void iow(unsigned int reg, unsigned int data) {
  IOWR(0x11000,0,0x01);
  usleep(20); //us
  IOWR(0x11000,1,0xFF);
}
  In the datasheet for DM9000A there are pins: iow (write), cs (chipselect), cmd (commad - index or data), sd0~7 (data)  In compare with C: iow = IOWR cmd = IO_ADDR or IO_DATA sd0~7 = reg or data in argument of function  So VHDL should be: 
iow &lt;= '0' -- active in low for writting
cs &lt;= '0' -- active in low
cmd &lt;= '0' -- i want to write index
... -- delay 10ns
sd &lt;= x"01" -- i want registry with offset 0x01
.. -- delay 20us
cmd &lt;= '1' -- i want to write data
... -- delay 10ns
sd &lt;= x"FF" -- i want set registry to value 0xFF
  And my questions are: What is correct way to implement this? How can I implement a delay like usleep() in C? Can I put this sequence in VHDL to some procedure?  I would be glad for your advice

altera_forum · Answer

Synthesizable VHDL has no concept of delays or sequential programming like in C.

Only things that can be implemented with sequential (flip-flops, RAM) and combinatory logic.

Therefore, you need to implement a state machine and counters to implement the delay.

Something like this:

process (clk) -- 100 MHz clock, 10 ns period

if rising_edge(clk) then

if state = state:1 then

iow <= '0'; cs <= '0'; cmd <= '0';

state <= state_2;

elsif state = state_2 then

sd <= x"02",

delay_counter <= 2000; -- 2000 * 10 ns = 20 µs

state <= state_3;

elsif state = state3 then

if counter = 0 then

state <= state_4;

else

counter <= counter - 1;

elsif state = state_4 then

cmd <= '1';

state <= state_5;

elsif state = state_5 then

sd <= x"FF;

...

end if;

end process

altera_forum · Answer

And is it appropriate to use a state machine with a lot of states if I have more these "register settings"? Or I should use for example procedure set_reg(reg,value)? I am afraid of its influence on the complexity of structure in FPGA.

altera_forum · Answer

As a first point, you should study the DM9000 bus timing requirements. Your above example won't work correctly, because it doesn't keep the IOW setup- and hold times. Using a state machine for the elementary read and write access sequence sounds reasonable. Most likely a second state machine should be responsible to schedule the command sequences.

altera_forum · Answer

FVM: In the attachment, there is a timing of DM9000A IOW, I suppose that there is a requirement for setup and holt time only in "sd" data case (10ns for setup and 3ns for hold)? And as you said - second state machine, do you thing something like this (example)? I think If I have a maximum delay 10ns, so one clk period with 50MHz frequency (T = 20ns) should be enough, right?  
IF (clk'EVENT AND clk = '1') THEN
         CASE state IS
            WHEN s0=&gt;
               IF input = '1' THEN
                  state &lt;= s1;
               ELSE
                  state &lt;= s0;
               END IF;
            WHEN s1=&gt;
               IF input = '1' THEN
                  state &lt;= s2;
               ELSE
                  state &lt;= s1;
               END IF;
            WHEN s2=&gt;
               IF input = '1' THEN
                  state &lt;= s0;
               ELSE
                  state &lt;= s2;
               END IF;
         END CASE;
      END IF;
   END PROCESS;
   
   PROCESS (state)
   BEGIN
      CASE state IS
         WHEN s0 =&gt;
            -- delay 10ns
         WHEN s1 =&gt;
            -- delay 20ns
         WHEN s2 =&gt;
            -- delay 5us
      END CASE;
   END PROCESS;
  * sorry for small image in the attachment, I haven't got enough of posts for url.

altera_forum · Answer

--- Quote Start ---

I suppose that there is a requirement for setup and holt time only in "sd" data case

--- Quote End ---

Your initial example is also violating T1.

There are some more points to consider, I won't elaborate a single detail now. If you want to squeeze DM9000 timing, you possibly should provide a faster clock for the state machine. Or implement double data rate output registers for some signals to achieve a finer timing control.

P.S.: I just realized the difference between DM9000 (which I previously used) and DM9000A. The timing has been considerably improved.

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How to implement a C routine to VHDL?

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