How to implement a C routine to VHDL?

Synthesizable VHDL has no concept of delays or sequential programming like in C.

Only things that can be implemented with sequential (flip-flops, RAM) and combinatory logic.

Therefore, you need to implement a state machine and counters to implement the delay.

Something like this:

process (clk) -- 100 MHz clock, 10 ns period

if rising_edge(clk) then

if state = state:1 then

iow <= '0'; cs <= '0'; cmd <= '0';

state <= state_2;

elsif state = state_2 then

sd <= x"02",

delay_counter <= 2000; -- 2000 * 10 ns = 20 µs

state <= state_3;

elsif state = state3 then

if counter = 0 then

state <= state_4;

else

counter <= counter - 1;

elsif state = state_4 then

cmd <= '1';

state <= state_5;

elsif state = state_5 then

sd <= x"FF;

...

end if;

end process