How to implement a C routine to VHDL?

FVM:

In the attachment, there is a timing of DM9000A IOW, I suppose that there is a requirement for setup and holt time only in "sd" data case (10ns for setup and 3ns for hold)?

And as you said - second state machine, do you thing something like this (example)? I think If I have a maximum delay 10ns, so one clk period with 50MHz frequency (T = 20ns) should be enough, right?

IF (clk'EVENT AND clk = '1') THEN
         CASE state IS
            WHEN s0=>
               IF input = '1' THEN
                  state <= s1;
               ELSE
                  state <= s0;
               END IF;
            WHEN s1=>
               IF input = '1' THEN
                  state <= s2;
               ELSE
                  state <= s1;
               END IF;
            WHEN s2=>
               IF input = '1' THEN
                  state <= s0;
               ELSE
                  state <= s2;
               END IF;
         END CASE;
      END IF;
   END PROCESS;
   
   PROCESS (state)
   BEGIN
      CASE state IS
         WHEN s0 =>
            -- delay 10ns
         WHEN s1 =>
            -- delay 20ns
         WHEN s2 =>
            -- delay 5us
      END CASE;
   END PROCESS;

* sorry for small image in the attachment, I haven't got enough of posts for url.