How to implement a C routine to VHDL?

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I suppose that there is a requirement for setup and holt time only in "sd" data case

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Your initial example is also violating T1.

There are some more points to consider, I won't elaborate a single detail now. If you want to squeeze DM9000 timing, you possibly should provide a faster clock for the state machine. Or implement double data rate output registers for some signals to achieve a finer timing control.

P.S.: I just realized the difference between DM9000 (which I previously used) and DM9000A. The timing has been considerably improved.