Altera_Forum
Honored Contributor
16 years agoHow to gracefully terminate the PCIe read request
I am using Stratix4 hardip in pcie gen1 x4 configuration. The hard IP has PCI bar register configured for 512K memory space. The Root complex is sending out the memory read request (non-posted) to the Stratix4 FPGA end point with valid address (that belongs to 512K memory block). The end point sends a request to the appropriate device behind it. But that device only supports smaller chunk of that 512K memory block. Thus it does not respond with data to the cycle eventhough it belongs to its memory range. Is it OK to send out completer abort TLP back to the root complex in such a situation? If not how to gracefully terminate such a cycle?
Thanks.