How to check Gain with ModelSim-ASE (FIR Compiler)

The worst-case gain depends on whether you want programmable coefficients or not.

For example, if you have 100 8-bit taps, then the worst-case gain is the sum of 100 0xFF values, i.e., a bit-growth of log2(100).

If your coefficients are fixed, then the worst-case bit-growth occurs for the worst-case signal made from sign(h[n]), where h[n] are your coefficients. This signal makes the FIR filter output peak sum(abs(h[n])).

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I want to 0db Gain result, but result is -6db

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FIR filters are generally designed to maximize the dynamic range, and then the "gain" is whatever, and you just deal with it, eg., by scaling the output to the nearest power of 2, or using a multiplier to apply gain, and then re-quantizing the result (via saturation and rounding). Depending on what you are filtering, you do not always know ahead-of-time what the output power in the band will be, so the filter output gain may need to be programmable.

Cheers,

Dave

Hi Dave,

Thank you for reply, I understood "I should reduce taps, and reduce bit-growth", "I should edit coefficients, and reduce sun(abs(h[n]))", and so on.

Excuse me, may I addition question?

If I designed to maximize the dynamic range, how to calucurate gain?

I think that input.txt and output.txt is voltage.

example

input bits : 8bit

input data : 100 ~ -100

bit-growth : 6.6 (log2(100))

output bits : 15bit

output data at one point : 25500 (sum of 100 0xFF values)

The following calculations correct?

Gain = 10 log (Vin / Vout)^2 = 10 log (100 / 25500)^2 = 48dB

It seems to be amplified.

or

I should convert out put max range into input data range (100 ~ -100) by user logic?

Thanks,

jas39

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Thank you for reply, I understood "I should reduce taps, and reduce bit-growth", "I should edit coefficients, and reduce sun(abs(h[n]))", and so on.

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No, that is not how you should think of the problem.

You need to first define what your signal is, eg., 8-bits from an analog-to-digital converter, and then define what your filtering requirements are, i.e., the pass-band ripple, stop-band rejection, and the transition bandwidth. Those parameters define your filter, which in turn defines the coefficients. At that point you know what the bit-growth will be. If the "answer" you get cannot be implemented, eg., you find that you cannot fit your filter into your FPGA, then you have to change your requirements and design a new filter.

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Excuse me, may I addition question?

If I designed to maximize the dynamic range, how to calucurate gain?

I think that input.txt and output.txt is voltage.

example

input bits : 8bit

input data : 100 ~ -100

bit-growth : 6.6 (log2(100))

output bits : 15bit

output data at one point : 25500 (sum of 100 0xFF values)

The following calculations correct?

Gain = 10 log (Vin / Vout)^2 = 10 log (100 / 25500)^2 = 48dB

It seems to be amplified.

or

I should convert out put max range into input data range (100 ~ -100) by user logic?

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Provide a specific set of filtering requirements, and I'll try to help walk you through a couple of design options. The "gain" of the filter will then be easier to understand.

Your description above is insufficient;

1. LPF

2. cut off frequency : 1.25MHz

3. input 8bit

4. ADC sampling frequency ???

5. Pass-band ripple requirement

6. Stop-band rejection requirement

Keep in mind that an FPGA can operate at 100MHz, so filtering the data to 1.25MHz results in a signal that is very "slow" compared to the clock rate of the FPGA. This fact can be exploited to reuse the FPGA hardware.

Cheers,

Dave

Hi Dave,

Thank you very much for reply.

Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP.

How about following requestments?

1. LPF

2. cut off frequency : 1.25MHz

3. input 8bit

4. ADC sampling frequency : 3MHz

( http://www.ti.com/lit/ds/symlink/adc1173.pdf

Does it need enough bigger than cut off frequency?)

5. Pass-band ripple requirement : 0.3dB

6. Stop-band rejection requirement : 40dB

Thanks,

jas39

Hi Dave,

Thank you very much for reply.

Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP.

How about following requestments?

1. LPF

2. cut off frequency : 1.25MHz

3. input 8bit

4. ADC sampling frequency : 3MHz

( http://www.ti.com/lit/ds/symlink/adc1173.pdf

Does it need enough bigger than cut off frequency?)

5. Pass-band ripple requirement : 0.3dB

6. Stop-band rejection requirement : 40dB

Thanks,

jas39

Hi Dave,

Thank you very much for reply.

Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP.

How about following requestments?

1. LPF

2. cut off frequency : 1.25MHz

3. input 8bit

4. ADC sampling frequency : 3MHz

( ttp://www.ti.com/lit/ds/symlink/adc1173.pdf

Does it need enough bigger than cut off frequency?)

5. Pass-band ripple requirement : 0.3dB

6. Stop-band rejection requirement : 40dB

Thanks,

jas39

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How about following requestments?

1. LPF

2. cut off frequency : 1.25MHz

3. input 8bit

4. ADC sampling frequency : 3MHz

( ttp://www.ti.com/lit/ds/symlink/adc1173.pdf

Does it need enough bigger than cut off frequency?)

5. Pass-band ripple requirement : 0.3dB

6. Stop-band rejection requirement : 40dB

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These do not make sense either. These sound more like parameters used to design an *analog* filter for feeding the ADC.

Why don't you explain what you are trying to do.

Cheers,

Dave

Regarding 0dB gain (unity) it is defined for a given reference frequency point e.g. dc for LPF.

It also affects signal mean power and final power depends how much power you chop off.

for dc unity gain set sum of coeffs to 1 (or sum of every single polyphase to 1 if upsampling)

Hi Dave and kaz,

Thank you very much for reply.

I don't understand the digital filter enough, so I'll think it over, and I will understand.

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I don't understand the digital filter enough, so I'll think it over, and I will understand.

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Lets see if this helps ... Above you say you want to sample a signal out to 1.25MHz, with an 8-bit ADC, right?

An 8-bit ADC has a signal-to-noise of around 8 x 6dB = 48dB. To ensure that your 1.25MHz signal is not corrupted by signals that alias into the band after sampling, your analog filter needs to reject signals by at least 48dB for the signals that will alias into the band. If your signal was filtered with an analog filter that was a simple RC filter, then the -3dB bandwidth of the filter needs to be about 5MHz to keep your passband ripple below 0.3dB. That single pole RC filter has a response amplitude of about -20dB at 50MHz and -26dB at 100MHz. If your ADC samples to 8-bits at 100MHz, then the signal from 50MHz to 100MHz will alias into your sampled band. This means that the signal from 100MHz-1.25MHz to 100MHz will alias onto your band of interest (as will all other higher frequencies). Since the power in that region is only down by 26dB, you will corrupt your signal, and be left with a signal-to-noise of only 26dB, which is about 26/6 ~ 4.3bits, so you've totally defeated using an 8-bit ADC.

The analog filter would actually be designed with a much faster roll-off than a single-pole response. The number of poles to use depends on how fast you can operate your ADC, and how many bits you want to preserve in your signal. From this discussion you can see that you often need to operate your ADC much faster than the Nyquist bandwidth of the signal you want to sample. Once you have sampled the signal, you can then use a *digital filter* to eliminate the out-of-band signal (the analog filter band edges) and then decimate the result to the Nyquist bandwidth of the signal, or perhaps slightly more than the Nyquist bandwidth. Your digital filter design depends on your "system" design.

Cheers,

Dave