Occasional ContributorHDMI RX: GXB rx_coreclkin and rx_pma_clk showing 600 MHz instead of 300 MHz (and failing timing)
I have an two-port HDMI RX-only design, with all the RX code copied from the example design. However, apparently there's something I didn't copy correctly because there is a 2x difference in the clock speeds shown in the Timequest report. My design is failing timing because it's showing the generated clocks to be 600 MHz instead of 300 MHz in the example design.
The "hdmi_clock_speed" screenshot shows the clock listings from the Timequest report (I've edited out irrelevant clocks and reordered a bit for clarity). In both designs, the HDMI RX clock is spec'ed at 300 MHz, but in my design the GXB rx_coreclkin and rx_pma_clk are generated at 600 MHz, whereas in the example design they show as 300 MHz. This causes my design to fail timing with regard to those clocks, although in practice everything works fine because the problem seems to be with regard to the compiler incorrectly deriving the speed of those clocks, rather than the circuit itself being wrong.
The "clk_warnings" screenshot shows one warning I get during compilation. Clearly, what the compiler is getting the wrong PLL settings somehow.
The "gxb_config" screenshot shows the first tab of the config of the GXB block in my design. As far as I can tell, nothing is changed from the example design. But obviously something, somewhere is different. Any suggestions of what it might be, or where to look?
