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NWein's avatar
NWein
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

HDMI RX: GXB rx_coreclkin and rx_pma_clk showing 600 MHz instead of 300 MHz (and failing timing)

I have an two-port HDMI RX-only design, with all the RX code copied from the example design. However, apparently there's something I didn't copy correctly because there is a 2x difference in the clo...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


There are 2 different IP that I am referring here.

  • NativePHY IP setting
    • I can see from your screenshot that you changed the default CDR reflclk from refclk 0 to refclk1 ?
    • What else did you changed ? You can slowly cross check back with HDMI example design
  • PLL IP setting
    • In HDMI example design, there are multiple PLL used to provide clocking to HDMI Rx IP and also NativePHY IP. Some are IOPLL IP and some are fPLL
    • The one connected to NativePHY IP should be fPLL.
    • Anyway, I advise you to trace back the clocking design connection in HDMI example design and cross check with your own design again


Thanks.


Regards,

dlim