HDMI RX: GXB rx_coreclkin and rx_pma_clk showing 600 MHz instead of 300 MHz (and failing timing)

I apologize that shortly after I opened this issue I got buried in other work and haven't been able to spend much (any?) time on this.

Regarding "default CDR reflclk from refclk 0 to refclk1": this change was recommended by Intel support as a means to get an RX-only design to work. That's the only change I made (at least, the only one I made intentionally). The entire block of HDMI RX code was copied from the reference design.

The two subfolders in the reference design that seem relevant are gxb_rx, and pll_hdmi. In both cases, I went in to look at the .xml files in my source tree, and compared them with a pristine copy of the reference design targeted at the dev board. So that's rtl/gxb/gxb_rx/gxb_rx.xml and rtl/pll/pll_hdmi/pll_hdmi.xml. In both cases, I found no significant differences other than the refclk changes mentioned above and various stuff related to changing the target device (we're using 10CX105YF672I5G vs. the dev board's 10CX220YF780E5G), and the different file locations. Nothing about PLL multipliers or dividers has changed.