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NWein's avatar
NWein
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

HDMI RX: GXB rx_coreclkin and rx_pma_clk showing 600 MHz instead of 300 MHz (and failing timing)

I have an two-port HDMI RX-only design, with all the RX code copied from the example design. However, apparently there's something I didn't copy correctly because there is a 2x difference in the clo...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI,


  1. May I know are you using Arria 10 or Cyclone 10 GX ?
  2. Which Quartus version ?
  3. Some possibility that I can think of that may affect clocking report are as below. You may want to cross check with example design again
  • NativePHY IP setting
    • PLL setting
    • SDC constraint


Thanks.


Regards,

dlim


  • NWein's avatar
    NWein
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    1) Cyclone 10GX

    2) Quartus Prime Pro 20.2

    3) a) Exactly where would I find the NativePHY PLL Setting? I've looked but can't find anything that obviously connects to the multiply by/divide by problem shown above.
    b) I will check again, but all the SDC constraints were copied directly from the example design, as was the entire source tree. Although obviously *something* is different, somehow..