HDL-master for SDRAM controller

Question

Hi,

I'm trying to connect my own hdl-master with DDR SDRAM Controller (MegaCore) for writing in off-chip memory. This UG (http://www.altera.com/literature/ug/ug_ddr_sdram.pdf) doesn't contain any information about basic avalon signals (write,writedata and etc.).

How I must to control this signals in my master? How the address space is allocated in controller?

For example, I attempted to write word of data in base controller address (without any offset) but it doesn't produce the expected result.

Thanks for any help.

altera_forum · Answer

The avalon specification is here (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).

Writing to the base address should work. Just remember that on an avalon master interface, the address is byte aligned, and not word aligned like on a slave interface.

altera_forum · Answer

Somewhere in this tutorial .zip file are a bunch of components written for Qsys (and SOPC Builder), two of which are read and write masters.  They should give you a good idea how to structure your logic:  http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html (http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html?)

Forum Discussion

HDL-master for SDRAM controller

2 Replies

Recent Discussions

About the System PLL in Agilex 5

Cyclone 10 GX Dev Kit: IOPLL not locking when using CvP mode

Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP

What Bank Mode of LPDDR5 does Agilex 5 support?

What is source clock of rx_core_clkout of Serial Lite IV IP