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Altera_Forum
Honored Contributor
Honored ContributorHDL-master for SDRAM controller
Hi, I'm trying to connect my own hdl-master with DDR SDRAM Controller (MegaCore) for writing in off-chip memory. This UG (http://www.altera.com/literature/ug/ug_ddr_sdram.pdf) doesn't contain ...
Altera_ForumHonored Contributor
Honored ContributorSomewhere in this tutorial .zip file are a bunch of components written for Qsys (and SOPC Builder), two of which are read and write masters. They should give you a good idea how to structure your logic: http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html (http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html?)
