Gate level simulation in ModelSim with DSP Builder generated designs

I try to further verify my design in DSP-Builder by applying gate-level simulation in Altera-ModelSim. But some modules which have no problems in RTL simulation do not work in the port-synthesis and gate-level simulation. I will try to describe my problems and would be grateful if someone could give some hints about how to fix it.

For instance, I have setup a counter in my DSP-Builder and can run the Simulink and rtl simulation on ModelSim without any problems. And then I run the full compilation in Quartus II to generate the vho and sdf files for post-synthesis and gate-level simulation in ModelSim. To do so, I also compile the altera_primitives_component.vhd into the altera library directory in ModelSim, so that I can compile the vho file into the work library. But then I get some warning messages when I run the post-synthesis simulation:

** Warning: (vsim-3473) Component instance "\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[1]\ : dffeas" is not bound.

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# ** Warning: (vsim-3473) Component instance "\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[2]\ : dffeas" is not bound.

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# ** Warning: (vsim-3473) Component instance "\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[3]\ : dffeas" is not bound.

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# ** Warning: (vsim-3473) Component instance "\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[4]\ : dffeas" is not bound.

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

# ** Warning: (vsim-3473) Component instance "\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[5]\ : dffeas" is not bound.

# Time: 0 ps Iteration: 0 Region: /tb_adder/dut File: C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder.vho

And my counter output become "UUUUUU".

When I try to run a gate-level simulation by further taking the sdf file into the simulation. Then I get the following error messages: ( my counter out is 8 bit, I get error for each bit port, but some messages are omitted here due to their similarities)

...

# ** Warning: (vsim-SDF-3250) C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder_vhd.sdo(1054): Failed to find INSTANCE '\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[5]\'.

# ** Warning: (vsim-SDF-3250) C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder_vhd.sdo(1089): Failed to find INSTANCE '\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[6]\'.

# ** Warning: (vsim-SDF-3250) C:/Work/Matlab/adder/tb_adder/simulation/modelsim/adder_vhd.sdo(1124): Failed to find INSTANCE '\auto_inst|adder_FPGA_0|Counter|Counteri|auto_generated|counter_reg_bit[7]\'.

# ** Warning: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).

My questions are:

What is my problem here, did I forget something?

It seems that modelsim have problem with "dffeas". But what is it?

How should I integrate my DSP-Builder design into my top-level design in Quartus II? Now I use the "export" option of the DSP-Builder Signal Compiler to export the vhdl files to my project and then instantiate my DSP-Builder design. But many modules seem not to be working in the post-synthesis or gate-level simulation , although everything is fine in rtl level simulation.

Many thanks for your helps!

Yang