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Altera_Forum
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16 years ago

Gate level simulation in ModelSim with DSP Builder generated designs

I try to further verify my design in DSP-Builder by applying gate-level simulation in Altera-ModelSim. But some modules which have no problems in RTL simulation do not work in the port-synthesis and ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Well, the problem is, the automatically generated tcl files does not compile the altera_primitives_components.vhd into the altera library, which is needed for the compilation of the vho file. So I just added this step to get the thing work.

As far as I know, NativeLink is not so flexible as using ModelSim directly. And I could not image if something does not work in ModelSim-AE will work with NativeLink.

Or you could provide me more details about the advantages of using NativeLink? Thank you!