FFT IP Core 8.1

I saw your code Omar. I would like to ask only about how you gave the inputs to sink_real.

Thanks

Mohammed

Hello everyone,

I have a problem with the FFT 8.1, too. I created an instance with the Megawizard. I chose a burst architecture with a single output, 1024 points, 16bit data width and 16bit twiddle width. I simulated and it works fine. BUT the goal is to connect the FFT instance to the Nios II.

Therefore I wrote a wrapper that matches the Avalon Streaming interface. I merged the 16bit imaginary and real signals to one 32bit bus at the input and the output. The exponent output, which is intended to be read after processing a block of e.g. 1024 points, can be read via an additional Avalon interface I added. So far so good.

I connected the FFT input and output to a FIFO each with a size of 1024 times 32bit. Between the FFT and the FIFOs I placed a timing adapter each, which adapts the read latency from 1 cycle (FIFO) to 0 (FFT).

FIFO --> Timing Adapter --> FFT (Wrapper)--> Timing Adapter --> FIFO

To prevent the FFT reading data from the FIFO everytime a 32bit value is written to it, the sink_ready signal of the FFT is ANDed with a signal, that is writeable by the processor.

The FIFO shall be written until it is full. Then the FFT sink_ready shall be released and the FFT shall read the 1024x32bit values in a burst until EOP is applied by the FIFO.

Problem:

If I write data to the FIFO, it outputs a SOP signal after the first data, because the Timing Adapter includes a small FIFO and is ready to receive data. This SOP is hold at the output of the timing adapter, also if the FFT does not apply a sink_ready. This makes the FFTinstance blocking, after it outputs several SOP's, until it is reset entirely. STRANGE!!!

The behavior can be seen in screenshot attached.

Has somebody an Idee how to solve this problem? Or has somebody a better solution to connect the FFT to the Nios II? Using SGDMAs is not a preferred solution, except somebody has a working solution. ...I tried this for weeks. :-(

I think that you can do the FFT Core and get the result easily using verilog. Then you can create a user component in the SOPC builder and passing the 32 bits to it which in turn will pass these 32 bits to the NIOS.

I hope this is useful.

I got the FFT 8.1 working with the Nios II!!!!

First of all, the OPTIONAL signal clockenable is not optional. If you do not add it via the Wizard and apply a fixed value of 1(high) to it, the generated IP-core will not behave like in the simulation. In my case the IP-core only accepted 7 times 32bit and than de-asserted the ready signal until it was reset.

I used a 1024points FFT with 16bit data width, Burst Architecture, a Single Output and "Add ClockEnable" checked. I wrote a wrapper around the created IP-core including two FIFOs and some status and control registers. The two 16bit inputs and outputs are merged. The 6bit Exponent Output which is required for scaling the results is readable via an additional Avalon-MM-slave Port.

I spend more than 14 days on this problem, because of the documantation of Altera...

I would like to ask you that why you need to do all that? You can only pass the source_real and source_imag to the NIOS.

In your simulation, can you take the NIOS code into your account?? or you only simulate the verilog code. I think you are using the waveform file for simulation purposes.