FFT IP Core 8.1

Hello everyone,

I have a problem with the FFT 8.1, too. I created an instance with the Megawizard. I chose a burst architecture with a single output, 1024 points, 16bit data width and 16bit twiddle width. I simulated and it works fine. BUT the goal is to connect the FFT instance to the Nios II.

Therefore I wrote a wrapper that matches the Avalon Streaming interface. I merged the 16bit imaginary and real signals to one 32bit bus at the input and the output. The exponent output, which is intended to be read after processing a block of e.g. 1024 points, can be read via an additional Avalon interface I added. So far so good.

I connected the FFT input and output to a FIFO each with a size of 1024 times 32bit. Between the FFT and the FIFOs I placed a timing adapter each, which adapts the read latency from 1 cycle (FIFO) to 0 (FFT).

FIFO --> Timing Adapter --> FFT (Wrapper)--> Timing Adapter --> FIFO

To prevent the FFT reading data from the FIFO everytime a 32bit value is written to it, the sink_ready signal of the FFT is ANDed with a signal, that is writeable by the processor.

The FIFO shall be written until it is full. Then the FFT sink_ready shall be released and the FFT shall read the 1024x32bit values in a burst until EOP is applied by the FIFO.

Problem:

If I write data to the FIFO, it outputs a SOP signal after the first data, because the Timing Adapter includes a small FIFO and is ready to receive data. This SOP is hold at the output of the timing adapter, also if the FFT does not apply a sink_ready. This makes the FFTinstance blocking, after it outputs several SOP's, until it is reset entirely. STRANGE!!!

The behavior can be seen in screenshot attached.

Has somebody an Idee how to solve this problem? Or has somebody a better solution to connect the FFT to the Nios II? Using SGDMAs is not a preferred solution, except somebody has a working solution. ...I tried this for weeks. :-(